The present invention relates to a layout method for semiconductor integrated circuits, and more particularly to a routing method for semiconductor integrated circuits such as application specific integrated circuits.
The semiconductor integrated circuits such as application specific integrated circuits (ASIC) may often be designed in the gate array approach or the standard cell approach. For the circuit design by the gate array approach or the standard cell approach, function cells realizing fundamental logics have previously been prepared in a design library for automatic placements of the function cells in support of computer aided design and subsequent automatic routing between the function cells to design the logic circuits.
FIG. 1 is a flow chart illustrative of the conventional automatic placement and routing method to be applied to large scale integrated circuits. In Step S30, schematic placement and routing are made in consideration of the length of wirings between the functional cells and density of the wirings. In the next Step S31, wiring loads are virtually found from schematic wiring information such as Manhattan length for executing a virtual load simulation to verify operation of the circuits. In the next Step S32, it is verified whether or not the required or intended functions are realizable and if realizable, then the process enters into the next Step S33 whilst if not realizable, then the process enters back into the former Step S30. In the Step S33, detailed placement and routing are made. In the subsequent Step S34, a resistance and a capacitance of the real wiring are calculated for execution of the real wiring simulation to verify the detailed operations of the circuits. In the Step S35, it is verified whether the required or intended functions are realizable and if realizable, then the layout processes will be completed whilst if not realizable, then the process enters back to the former step S33.
FIG. 2 is a diagram illustrative of the conventional routing layouts in detail. First level interconnection channels 1A, 1B, 1C, 1D, 1E and 1F extend in the row direction at a first constant pitch "d1". Second level interconnection channels 2A, 2B, 2C, 2D, 2E and 2F extend in the column direction at a second constant pitch "d2". The second level interconnection channels 2A, 2B, 2C, 2D, 2E and 2F extend in the vertical direction to the first level interconnection channels 1A, 1B, 1C, 1D, 1E and 1F. First level interconnections 11, 12, 13, 14, 15 and 16 are provided which extend on the first level interconnection channels 1A, 1B, 1C, 1D, 1E and 1F respectively. Second level interconnections 21, 22, 23, 24, 25 and 26 are provided which extend on the second level interconnection channels 2A, 2B, 2C, 2D, 2E and 2F respectively. The first level interconnections 11, 12, 13, 14, 15 and 16 are aligned in the first pitch "d1" whilst the second level interconnections 21, 22, 23, 24, 25 and 26 are aligned in the second pitch "d2". Through holes 31 and 32 are provided which connect the first interconnections 11, 12, 13, 14, 15 and 16 and the second interconnections 21, 22, 23, 24, 25 and 26.
As in the recent years micro-lithography techniques have been developed which make it possible to reduce the with and pitch of the interconnections down to 1 micrometers respectively. The reduction in pitch between the interconnections in the same level raises the serious problem with increase parasitic capacitance between the adjacent interconnections. If two adjacent interconnections of 1 micrometer in width and of 1 micrometer in thickness are aligned in a pitch of 1 micrometer over a silicon oxide film having a thickness of 2 micrometers formed over a silicon substrate and further a silicon oxide inter-layer insulator is formed which extends over the interconnections and over the silicon oxide film over the silicon substrate, then a total capacitance of a single signal interconnection is 0.24 pF/mm whilst the parasitic capacitance of between the adjacent two interconnections is 0.14 pF/mm. This means that the parasitic capacitance between the adjacent two interconnections is 60% of the total capacitance of the single signal interconnection. This results in time delays of signal transmission on the interconnection. This limits high frequency performance of the integrated circuits. If the desired high frequency performance can not be obtained, the Step S33 of the placement and routing processes should be made frequently until the desired high frequency performance can be obtained.
In order to settle the above problem, it was proposed in the Japanese laid-open patent publication No. 4-333980 to execute placement and routing processes frequently so that the length of the interconnections of a delay-value maximum net is possibly shortened. FIG. 3 is a flow chart illustrative of the other conventional layout method. In the Step S40, circuit diagrams of the semiconductor integrated circuits are inputted. In the next Step S41, circuit operations are simulated without consideration of resistance and capacitance of the interconnections for subsequent storing data as the results of a virtual simulation. In the Step S42, automatic placement and routing of function cells are executed. In the Step S43, circuit operations are simulated in consideration of the resistance and capacitance of the interconnections as a real simulation. In the next Step S44, there is made a compression between the above virtual simulation made without consideration of resistance and capacitance of the interconnections and the real simulation made in consideration of resistance and capacitance of the interconnections to verify whether the delay in time of signal transmission on the interconnections is sufficiently small or not. If sufficiently small, then the layout processes have been completed and if not sufficiently small, then the layout processes enters into the Step S45. In the Step S45, an interconnection causing a maximum delay in time of signal transmission is extracted. In the subsequent Step S46, a priority file is prepared wherein the highest priority is assigned to the placement order of the interconnection pattern causing the maximum delay in time of the signal transmission. In the Step S47, it is verified whether the delay in time to the signal transmission obtained by the comparison of the virtual and real simulations is smaller than the past delay in time the signal transmission. If larger than the past delay, then the layout processes have been completed. If, however, of the delay is smaller than the previous delay, the layout processes enter into the Step S48. In the Step S48, it is confirmed whether the number of repeats is within a predetermined number and if within the predetermined number, then the layout processes returns back to the Step S42 so that the automatic placement of the interconnection patterns are made in accordance with the order of priority. If, however, the number of repeats exceeds the predetermined number, then the layout processes have been completed.
The above conventional layout method has the following disadvantages, particularly when the interconnections are scaled down. If the pitch of the interconnections is reduced, then the parasitic capacitance between the two adjacent interconnections exceeds the capacitance of the individual interconnection, for which reason even if the capacitance of the individual interconnection is reduced by reduction in length of the individual interconnection by the above layout process, then it is no longer possible to obtain a sufficient reduction in the total capacitance of the parasitic capacitance between the two adjacent interconnections and the capacitance of the individual interconnection. This results in an increase in the number of repeating the placement and routing processes to shorten the individual interconnections. In order to reduce the repeating of the placement and routing processes, it is required to make a design in consideration of sufficient margin. This, however, results in lowering the degree of integration of the semiconductor circuits and in increase in the area of the chip.
Still another conventional layout method was proposed and disclosed in the Japanese laid-open patent publication No. 2-68933, wherein the pitch of the interconnections is fixed whilst the width of the interconnections is optimized so that the delay in time of the signal transmission is minimized under the condition that the length of the interconnections has the maximum. FIG. 4 is a fragmentary lane and cross sectional views illustrative of the layout of the interconnections in the above layout method. Interconnections 41 are provided which extend in parallel to each other and within an insulation film 42 formed over a semiconductor substrate 43. The interconnections 41 have a thickness of "T" and a width of "W". The interconnections 41 are aligned at a pitch of "P" and a distance "S" between them. The thickness of the insulation layer 42 between the bottoms of the interconnections 41 and the top surface of the semiconductor substrate 43 is defined as "H". The pitch "P" of the interconnection is fixed. Assuming that the length of the interconnections has the maximum, the width "W" of the interconnection is analyzed in consideration of the resistance and capacitance of the interconnections so that the delay in time of the signal transmissions on the interconnections is minimum.
The above layout method has the following disadvantages. If the pitch of the interconnections is fixed to be narrow, then the influence of the parasitic capacitance between the adjacent two interconnections dominates the capacitance of the individual to interconnection whereby it is difficult to obtain a sufficient reduction in total capacitance of the interconnections. This results in an increase in the delay in time of the signal transmissions. Under the condition of narrower pitch of the interconnections, it is difficult to find out the optimum width of the interconnections. Widening the pitch of the interconnections is essential to obtain a sufficient reduction in time delay of signal transmissions on the interconnections.
Under the above circumstances, it had been required to develop a novel layout method which enables the time for layout process to be shortened and allows a high density integration or scaling down the semiconductor integrated circuits.